Strategies from the engineers at Moetion Technologies
Your design is done. Your customers are eager. Pre-orders are in.
Now comes the part most product teams underestimate: making sure that every unit coming off the line actually works. For teams that haven’t navigated end-of-line test strategy before, the options are genuinely overwhelming. Testing can happen after every fabrication step or only at the very end. It can be fully automated, semi-automated, or manual. And each test type catches a different class of problems.
Getting this wrong has real consequences. Too little testing means defective products reach customers. Too much testing, or the wrong kind, means you’ve bought expensive equipment that slows your line and doesn’t meaningfully increase quality.
This guide walks through how our team at Moetion Technologies thinks about EOL test strategy: what the main test types are, when each one earns its place, and how to build a strategy that scales with your volume.
Why PCB End-of-Line Test Strategy Requires Attention
Even with an excellent design and a capable Contract Manufacturer, PCB assembly introduces variation. Paste deposits vary slightly. Components shift during reflow. Solder joints that look clean can be suspect. Components from different lot dates can behave differently under load. None of these failures are anyone’s fault — they are inherent to the physics and tolerances of the manufacturing process. The only way to catch them reliably is to test for them.
The other reason test strategy matters is economics. A defect caught early reduces your scrap costs. The same defect caught after SMT, hand assembly, programming, conformal coating, and final assembly has accumulated every one of those process costs on top of it. The math strongly favors catching defects early, but only up to the point where the cost of testing exceeds the cost of letting the defect proceed. Finding that balance is what a good test strategy does.
The Right Way to Think About It
At Moetion Technologies, our philosophy around end-of-line testing comes down to three principles:
- Understand what testing will be done no matter what
- Determine what additional failures each incremental test step would actually catch
- Balance the cost of delayed defect detection against the cost of the test itself
Start by mapping out the tests you are certain you have to do, and go from there. Typically, that starts with an end-of-line functional test after the unit is fully assembled. This makes sure a customer is happy with the product received. Even if you’ve tested at every single step along the way, a final functional test is needed to make sure that as it was fully assembled, no new defects such as pinched wires or forgotten assembly steps.
The second principle guards against the instinct to add tests because they exist, not because they add coverage. Doing ICT after AOI on a simple, low-density board likely will catch very little that AOI didn’t already flag. If the incremental defect catch is small, the test probably isn’t worth its cost.
The third is about timing. Every step you add to a product before the point of test adds cost that gets scrapped when a defect is found. But if your volumes are low and the test required to catch that defect earlier costs more than the scrap, accepting the delayed detection may be the right financial call.
| Our Recommendation Treat test strategy as a design decision, not a manufacturing decision. The time to figure out what tests you need is during PCB layout, not after your first panels arrive. Test point placement, component accessibility, and board panelization all affect what tests are even possible, and none of them can be changed without a re-spin. |
Building Your Test Baseline
Before you can decide which tests to add, you need to know what you’re working with. We use this checklist to build out the picture:
- List every assembly step required to build the product, from bare PCB through final packaging.
- Estimate the line rate and cycle time at each assembly station.
- Estimate the material and labor cost accumulated at each step — this tells you what’s at stake when a defect is found at each point in the line.
- Identify the tests that must happen regardless of strategy (typically, at minimum, a final functional test).
- Map when in the assembly process those mandatory tests occur.
- Identify the gaps: what failure modes aren’t covered between your mandatory tests?
- Research the throughput and cost of test options that could close those gaps.
This exercise often surfaces something useful: teams tend to either over-test simple boards or under-test complex ones, because they’re matching a test to a general category rather than to their specific failure modes. Working through the assembly cost stack forces the conversation to be about economics, not instinct.
Understanding Test Types
There are more test options than most product teams realize, and they vary significantly in what they catch, how fast they run, and what they cost to implement. Test equipment can be thought of in 3 distinct categories:
- Re-usable and automated: SPI, AOI, X-ray, and Flying Probe
- Custom fixture but re-usable equipment: programming stations, ICT, JTAG
- Custom fixture and test software: function bed-of-nails and final functional testing
Expand the descriptions below to learn more about each test type.
Before any components are placed, the bare PCB can be tested for opens and shorts between nets using a bed-of-nails fixture or flying probe. This catches fabrication defects before any assembly cost is added. Testing can be done on every board, or on a sampling basis. Many CMs include it in their standard process; confirm this with yours before assuming.
| Best for: Catching fabrication defects before any component cost is at stake. Should be a baseline for all programs. |
SPI uses a camera and laser system to measure solder paste deposits on each pad before components are placed. It catches volume, area, and offset errors that are invisible to the eye but lead directly to solder joint failures after reflow. An industry contact recently told us that >85% of their end-of-line defects were related to solder paste issues, pushing them to install an SPI machine.
SPI equipment is expensive to own outright, but most full-service CMs have it in-line. The key is making sure your CM actually uses it and reviews the results. An SPI machine that produces a pass/fail log no one looks at is not doing its job.
| Best for: Any SMT assembly program. The cost per defect caught is extremely low when placed before the reflow oven. |
AOI scans assembled boards with high-resolution cameras, comparing placement, orientation, and solder joint appearance against a reference. It’s fast, non-contact, and catches a wide range of assembly defects: missing or wrong components, reversed polarities, lifted leads, solder bridges, and tombstoning.
Source: PCBgogo
AOI is typically run post-reflow and sometimes post-wave solder. It’s one of the most broadly applicable tests in electronics manufacturing, and when combined with SPI, it covers the large majority of assembly defects on most board types. Modern AOI systems are increasingly AI-assisted, which has meaningfully reduced false-positive rates that historically made AOI outputs difficult to act on quickly.
One important limitation: AOI can only see what the camera can see. Hidden solder joints under BGA, QFN, or other bottom-terminated packages are invisible to it. If your design uses these packages, AOI needs to be paired with X-ray.
| Best for: Nearly every SMT program as a baseline. Pair with SPI for comprehensive pre-and-post reflow coverage. |
ICT uses a custom fixture — typically a bed-of-nails — to contact test points on the board and measure individual components and nets. It can verify component values, check for opens and shorts, and measure signal integrity across critical nets. When test point coverage is adequate, ICT can intercept roughly 70–90% of manufacturing defects before any functional testing occurs.
The two most important things to understand about ICT: it requires a custom fixture, and that fixture requires accessible test points designed into the PCB layout. The fixture typically costs $3,000–$15,000+ depending on board complexity, and changes to the board design may require fixture updates. This makes ICT volume-dependent — at low volumes, the amortized cost per unit is rarely justified. At mid-to-high volumes, it often is.
Source: AllElectroHub
Warning: CM’s often demand 100% ICT coverage, meaning a test point on every single individual node of the design. This is usually impractical or at times impossible and can introduce EMC failure modes on high-speed buses. Be prepared to push back with justifications why some nodes can be skipped or combined.
| Best for: Mid-to-high volume programs where fixture cost is justified by defect reduction and scrap avoidance. |
Flying probe is the flexible alternative to ICT. Instead of a fixed bed-of-nails fixture, robotic probes move across the board and contact pads, vias, and component leads directly. There’s no custom fixture, which means no fixture cost and no layout requirement for dedicated test points. However, there is typically NRE to program the machine.
The tradeoff is speed. Flying probe is slower than ICT because each probe contact is made sequentially rather than simultaneously. For prototype and low-volume work, this is fine — the absence of fixture cost more than compensates. For high-volume production, the throughput impact rules it out unless the product is complex enough that ICT coverage would be severely limited by layout constraints anyway.
Source: WeVolver
Flying probe is also the right answer for boards with dense component placement that doesn’t leave room for ICT test pads — a common situation with modern miniaturized designs. Some flying probe systems can also apply power and run simple functional checks, which extends their coverage beyond what traditional ICT achieves.
| Best for: Prototype and low-volume production, and any program where ICT test point access is constrained by layout density. |
X-ray is the only method that can image solder joints hidden under components. It’s essential for any board that uses BGAs, QFNs, LGAs, or similar packages where the solder connections are invisible from above. X-ray inspection can identify voids in solder balls, bridging, and joint collapse — failure modes that AOI and ICT simply cannot reach.
X-ray is not typically run on every unit. For most programs, it’s used during process setup and qualification to establish that the reflow profile and paste stencil are producing acceptable joints, and then spot-checked periodically or used to diagnose field failures. Full 3D automated X-ray inspection (AXI) is available for high-reliability programs where inspection of hidden solder joints on every unit is warranted.
| Best for: Any program with BGA, QFN, or bottom-terminated components. Process qualification and field failure analysis on all programs. |
Functional testing applies power to the board and verifies that it behaves as intended. It’s the test type closest to what a customer experiences, and it’s the only method that validates the product’s actual function. Testing can be done in a PCBA fixture or in a fully assembled product, and approaches may include:
- Self-test: firmware running on the device’s own microcontroller checks internal peripherals, memory, and interfaces. Fast and zero fixture cost, but limited to what the software can observe.
- Boundary Scan (JTAG): a somewhat legacy approach but it is still used for some applications
- Intermediate functional test: a mid-line test station applies power and stimulus signals to verify key functions before final assembly steps are complete. A programming station can often double as this, checking critical nets through the microcontroller while it flashes firmware.
- Simulated-use functional test: a test fixture that replicates real-world inputs and loads. The closest analog to actual customer use. Slower to develop but the highest coverage for system-level behavior.
- Full-unit: after final assembly, the full unit is tested. This may include all it’s key functions, or just the functions that could be impacted by defects introduced by the final assembly steps
| Our Recommendation A final functional test before shipment is usually non-negotiable, regardless of what other tests precede it. Even if you’ve tested at every step along the way, final assembly steps can introduce new failure modes: pinched wires, missed assembly steps, loose connectors. The final functional test is the last gate before your customer. |
Recommendations by Volume Tier
The right test stack is heavily dependent on your production volume. Here’s how we think about it:
| Volume tier | Recommended test stack | Why |
| Low (<10k/yr) | SPI + AOI + Functional (intermediate + final) | Fixture costs exceed scrap savings. Camera-based inspection catches >85% of defects. Use programming station as dual-purpose intermediate test. |
| Mid (10k–50k/yr) | SPI + AOI + Offline ICT + Functional (simulated use + final) | Offline ICT fixture justifies itself. Catches >90% of PCBA defects before manual steps add cost. Final functional test validates closed-loop behavior. |
| High (>50k/yr) | SPI + AOI + Inline ICT + Functional (self-test + full product) | Inline ICT maximizes throughput. ICT must run <30 sec so excludes power/functional checks — a dedicated functional station covers what ICT can’t. |
A note on the programming station
At any volume, a firmware programming station is required if your product runs software. Don’t treat it as just a programming step. With modest effort, that station can verify critical nets, check communication interfaces, and confirm power rail behavior using the onboard microcontroller — turning a necessary step into a dual-purpose test asset. This is especially valuable at low volumes where additional test fixtures are hard to justify.
The Step Most Teams Miss: Design for Testability
Design for Testability (DFT) is the set of decisions made during PCB layout that determine what can actually be tested in manufacturing. The most important of these is test point placement. ICT and functional test fixtures contact the board through test points, and if those test points aren’t in the layout, the fixtures can’t be built — or they’re built with significantly reduced coverage.
Key DFT guidelines worth knowing before layout begins:
- Space test points 4mm apart to give space between pogo-pins
- Keep test points on the primary (component) side of the board when possible. Double-sided fixtures are more expensive and slow cycle time.
- Avoid placing test points under components or in areas with tall adjacent parts. Probes need clearance.
- Include tooling holes for fixture alignment — two in diagonal corners at minimum. Without them, fixtures are built with custom cradles that add cost and reduce accuracy.
- For designs with BGA or QFN components, route JTAG/boundary scan connections to a dedicated header or test point cluster. This provides a path to test hidden connections without X-ray.
Bottom side Test Points on a Moetion-designed PCB
The decisions above are invisible in EDA design rule checks — your layout tool won’t flag a missing test point. But they directly determine the ceiling of your test coverage and the cost of your fixtures. The best time to address them is during DFM review, before the first panel is built. Changes after the fact mean a board re-spin.
| Our Recommendation Ask your CM for their DFT guidelines before layout begins, not after. Every CM has specific requirements for test point size, spacing, and clearance based on the fixtures they operate. Matching your layout to those requirements from the start is far cheaper than discovering the mismatch during fixture build. |
Final Thoughts
End-of-line test strategy is one of those topics that feels like an operations detail but is actually an engineering decision with direct product quality and financial implications. The teams that handle it well almost always have one thing in common: they thought about it during design, not during production setup.
Every program is unique and has slightly different test needs, but the framework is straightforward: start with the tests you must do regardless, add tests where the incremental defect coverage justifies the cost, and make sure your board layout supports the tests you’ve planned. Get the volume-to-test-stack match right, build DFT into your layout process, and use your programming station as a dual-purpose test asset wherever you can.
If you’re working through a test strategy for an upcoming program and want a second opinion, our team at Moetion Technologies is happy to talk. Reach out at moetiontech.com/contact.